SyDPy Roadmap

Some of many features that will be included into the SyDPy soon:

• Speed optimization

• Full manual

• Manual for developers

• Conversion to Verilog

  Proof of concept already done. Some testing and wrapping up left.

• Cosimulation with Verilator

  Proof of concept already done. Some testing and wrapping up left.

• Constrained-random sequences generation by SystemC SVC

  Proof of concept already done. Some features left to implement, testing and wrapping up.